1. Field of the Invention.
The present invention relates to electronic semiconductor devices and fabrication methods, and more particularly, to Schottky barrie diodes including diodes formed in integrated circuits.
2. Description of the Related Art.
Schottky barrier diodes are widely used in integrated circuits in applications such as decoupling devices in digital circuits (silicon bipolar and gallium arsenide MESFET) and as clamping devices to prevent heavy saturation of bipolar transistors. See, for example, A. Milnes, Semiconductor Devices and Integrated Electronic .sctn. 2.5 (Van Nostrand Reinold 1980) and S. Sze, Physics of Semiconductor Devices .sctn. 5.6 (Wiely-Interscience 2 d Ed 1981). Generally, a Schottky barrier diode is formed by deposition of suitable barrier metal into a contact opening through a silicon dioxide sulating layer down to bare silicon. The barrier metal may be reacted with the silicon to form a silicide-to-silicon junction (for example, Pt is deposited and reacted to form PtSi and is used as a high barrier diode on n-type silicon for biplor transistor clamping, and Ti is deposited and reacted to form TiSi.sub.2 and is used as a low barrier diode for logic circuits) or may be left unreacted and form a metal-to-silicon junction (for example, TiW is used as a low barrier diode and Al as a high barrier diode on n-type silicon). Note that the reaction-formed silicide may be self-aligned because of the reaction with silicon: that is, a metal is uniformly deposited but only the portion in contact with bare silicon reacts so the unreacted metal away from the silicon can be selectively removed. Of course, a silicide could be directly deposited which would avoid the need for reaction of the metal with the silicon but would not yield a self-aligned structure.
The specific contact resistivity for a metal-to-heavily dope silicon junction is approximated by: ##EQU1## with .phi. the metal-silicon barrier height, N the doping concentration, m the carrier effective mass, and .epsilon. the dielectric permittivity of silicon; so degenerately ddoped (either p or n) silicon will form an ohmic junction with a metal.
The development of bipolar VLSI circuits, such as gate arrays and signal processors, requires Schottky barrier diodes with high performance but with small size. Effects such as series resistances and parasitic p-n junctions must be minimized, and as devices are scaled down, the reduction of size of a Schottky barrier clamp diode becomes increasing difficult without the concurrent reduction of clamp efficiency and increase of series resistance to levels that significantly degrade circuit performance.
Various approaches to down-scaling Schottky barrier diodes include a self-aligned guard ring clamp diode structure in Y. Okada et al, A New "SICOS" Schottky Device, 1985 IEEE IEDM Tech. Dig. 38 and guard ring-less VSi.sub.2 Schottky barrier diodes in V. Drobny, Nearly Ideal Unguarded Vanadium-Silicide Schottky-Barrier Diodes, 33 IEEE Tr. Elec. Dev. 1294 (1986). The avoidance of a guard ring may also be accomplished by moat etching to reduce field crowding at the periphery at the barrier metal; see C. Rhee et al, Moat-Etched Schottky Barrier Diode Displaying Near Ideal I-V Characteristics, 15 Soild State Elec. 1181 (1972). The moat etching also reduces the series resistance due to the thinning of the silicon.
However, these approaches fail to overcome the problems of the known Schottky barrier diodes of increase in series resistance and decrease in clamp efficiency due to the down-scaling of the diode.